1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and a Chemical Mechanical Polishing (CMP) apparatus employed therein, more particularly to a method and an apparatus using a damascene CMP process that prevents a so-called xe2x80x9cdishing problemxe2x80x9d in producing a buried wiring line.
2. Description of the Related Art
In LSI (Large Scale Integrated) circuits such as microprocessors, memories and a like, there is substantial incentive toward higher levels of integration density and design rules permitting smaller minimum feature sizes for individual circuit components or devices. In other words, as a semiconductor industry moves toward smaller and smaller device dimensions, a greater density of devices per silicon substrate is required. As the device dimensions shrink, width of wiring trenches or holes formed in insulation films also shrinks. Further, since wiring density has increased as described above, a so-called xe2x80x9cmultilevel metallization technologyxe2x80x9d has been developed, wherein a plurality of layers each of which is provided with a wiring line and a thickness are stacked together into a stack to form a semiconductor device.
In LSI circuits described above, such narrow dimensions of wiring lines lead to higher resistances, and therefore affect devices in their characteristics such as operation speeds and a like. Consequently, it is required to reduce resistance in the wiring lines. As conventional wiring materials for semiconductor devices such as LSI circuits and a like, there are aluminum (Al) or aluminum-based alloys, which are excellent in electric properties and workability. However, the aluminum-based alloys are poor in resistance to electro-migration and stress-migration. Under such circumstances, there are increasing tendencies to use copper (Cu) or copper-based alloys in place of the aluminum-based alloys since the copper-based alloys are excellent in resistance to electro-migration and stress-migration and smaller in electric resistance than the aluminum-based alloys.
On an other hand, as one of conventional structures adapted for use with a fine wiring line, there is a damascene wiring structure in which a trench for forming the wiring line (hereinafter referred to as a wiring line trench) is formed in an insulation film, and filled with metal to produce a buried wiring line. FIG. 7 is a sectional view of a silicon substrate, illustrating a typical damascene structure. For example, as shown in FIG. 11 in which the dishing 57 is exaggerated, an insulation film 52 which is constructed of a silicon oxide film is formed on a top surface of silicon substrate 51. In the insulation film 52, a wiring line trench 53 is previously formed. A copper film 55 is formed in the wiring line trench 53 through a barrier metal film 54 made of tantalum (Ta), so that a buried wiring line 56 constructed of these films 54, 55 is formed. The buried wiring line 56 has its surface polished to a flat mirror finish by a well-known CMP process. In the buried wiring line 56, the barrier metal film 54 serves as a diffusion barrier film to prevent electro-migration of copper from the copper film 55 to the insulation film 52 and further to the silicon substrate 51 through the insulation film 52.
With reference to FIGS. 8A, 8B and 8C, a conventional method of manufacturing a semiconductor device will be now described step by step.
First, as shown in FIG. 8A, for example, the insulation film 52, which is constructed of a silicon oxide film or a like, is formed over an entire surface of the silicon substrate 51 by a chemical vapor deposition (CVD) process or a like. Then, by using a well-known photolithographic process, the wiring line trench 53 is formed in the insulation film 52 to reach some midpoint in depth of the insulation film 52. After that, as shown in FIG. 8B, by using a sputtering process or a like, the barrier metal film 54 (made of tantalum) and the copper film 55 are sequentially formed in this order over the entire surface of the silicon substrate 51 through the insulation film 52 provided with the wiring line trench 53.
Then, the silicon substrate 51 is transferred to a CMP unit for performing the CMP process. Using this CMP unit, as shown in FIG. 8C, the copper film 55 formed on an uppermost surface of the barrier metal film 54 is removed by polishing. Then, as shown in FIG. 11, the copper film 55 and the barrier: metal film 54 both formed on the silicon substrate 51 is removed by polishing, so that the buried wiring line 56 is formed, whereby the semiconductor device is completed, wherein the dishing 57 is shown in exaggerated form for clarification.
FIG. 9 shows a cross-sectional view of the conventional CMP unit 60 used in the CMP process described above. As shown in FIG. 9, the conventional CMP unit 60 is provided with a polishing platen 61 to which a polishing pad 62 is attached. The polishing pad 62 is brought into contact with a surface of the silicon substrate 51 being polished. In operation, the polishing platen 61 is rotatably driven through its rotating shaft 63 in a condition in which a polishing or abrasive liquid is supplied from an abrasive liquid supply nozzle 64 onto the polishing pad 62 and retained thereon.
On an other hand, as is clear from FIG. 9, a pressure unit 65 for holding and forcing the silicon substrate 51 being polished is disposed above the polishing platen 61. The pressure unit 65 is provided with a metal head 66 and a retainer 67 on which the metal head 66 is fixedly mounted. These components 66, 67 of the pressure unit 65 define a space for receiving therein an air bag 68. The air bag 68 serves as a flexible element, is brought into press-contact with a rear surface of the silicon substrate 51, and functions to force the silicon substrate 51 against the polishing pad 62 which is rotatably driven when the pressure unit 65 is rotatably driven by its rotating shaft 69.
In a polishing operation in which the conventional CMP unit 60 shown in FIG. 9 is used: first, the silicon substrate 51 which is still in the step of FIG. 8B has its top surface brought into contact with the polishing pad 62; and then, the abrasive liquid is supplied from the abrasive liquid supply nozzle 64 onto the polishing pad 62 in a condition in which both the polishing platen 61 and the pressure unit 65 are rotatably driven; whereby the copper film 55 of the silicon substrate 51 is polished, as shown in FIG. 8C. In this case, since the air bag 68 which is large in elastic deformation is used to force a front surface of the silicon substrate 51 against the polishing pad 62 of the polishing platen 61 during the polishing operation, it is possible to polish a top surface of the copper film 55 to a flat mirror finish (shown in FIG. 8C). In the conventional case, a same polishing operation is repeatedly performed to form the buried wiring line 56 of the semiconductor device (shown in FIG. 11 in which the dishing 57 is exaggerated) until the barrier metal film 54 formed on an uppermost surface of the insulation film 52 of the silicon substrate 51 is completely removed.
As described above, when the barrier metal film 54 and the copper film 55 both formed on the top surface of the silicon substrate 51 through the insulation film 52 are removed by the CMP process to form the buried wiring line 56 in the conventional method of manufacturing the semiconductor device, the same pressure unit 65 is repeatedly used in individual process steps for polishing the copper film 55 and for polishing the barrier metal film 54 in a condition in which the air bag 68 continuously forces the front surface of the silicon substrate 51 against the polishing pad 62 of the polishing platen 61.
As is clear from the above, in the conventional method of manufacturing the semiconductor device, since the same pressure unit 65 is used in polishing the barrier metal film 54 in a condition in which the air bag 68 forces the silicon substrate 51 against the polishing pad 62, the copper film 55 is also polished and partially removed to cause a dishing problem (shown in FIG. 11). More specifically, when the copper film 55 and the barrier metal film 54 are polished by the CMP process using the same pressure unit 65, ratio of the removal rate, of the copper film 55 to removal rate of the barrier metal film 54 tends to decrease. Due to this, the copper film 55 is also polished when the barrier metal film 54 is polished. As a result, as shown in FIG. 11, the dishing 57 is formed in the top surface of the copper film 55. In case that the plurality of trenches each having a narrow width are formed in the area of the surface of the insulation film 52 so as to be spaced apart from each other at predetermined intervals and filled with copper to form a plurality of copper films 55 in the area, the area tends to cause erosion 58 in which the entire surface of the area is formed into a dish-like shape when subjected to the CMP process.
As described above, a phenomenon that the ratio of the removal rate of the copper film 55 to the removal rate of the barrier metal film 54 reduces occurs not only in cases where the pressure unit 65 (shown in FIG. 9) provided with the flexible element or air bag 68 which is large in deformation is used, but also in cases where a pressure unit 75 (shown in FIG. 10) provided with a flexible element which is small in deformation and constructed of a metal plate 70 made of stainless steel or like metal is used.
In view of the above, it is an object of the present invention to provide a method of manufacturing a semiconductor device and an apparatus for performing a chemical mechanical polishing process employed in the above method, which is capable of, preventing a copper film from being over-polished when a barrier metal film is polished by the chemical mechanical polishing process for producing a buried wiring line.
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein after a trench for a wiring line is formed in an insulation film covering a surface of a semiconductor substrate, a first and a second metal film are subsequently formed over an entire surface of the insulation film including the trench; and, the first and the second metal film formed on a top surface of the semiconductor substrate through the insulation film are subsequently polished by a chemical mechanical polishing process to form a buried wiring line, the method including:
a first polishing step for polishing the second metal film in a condition in which a polishing liquid is supplied to a polishing platen, and the semiconductor substrate having its surface forced against the polishing platen is brought into press-contact with a first flexible element which is large in deformation; and
a second polishing step for polishing the first metal film in a condition in which a polishing liquid is supplied to the polishing platen, and the semiconductor substrate having its surface forced against the polishing platen is brought into press-contact with a second flexible element which is small in deformation.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein after a trench for a wiring line is formed in an insulation film covering a surface of a semiconductor substrate, a first and a second metal film are subsequently formed over an entire surface of the insulation film including the trench; and, the first and the second metal film formed on a top surface of the semiconductor substrate through the insulation film are subsequently polished by a chemical mechanical polishing process to form a buried wiring line, the method including:
a first polishing step for polishing the second metal film in a condition in which a polishing liquid is supplied to a polishing platen, and the semiconductor substrate having its surface forced against the polishing platen is brought into press-contact with a first pressure unit provided with a first flexible element which is large in deformation; and
a second polishing step for polishing the first metal film in a condition in which a polishing liquid is supplied to the polishing platen, and the semiconductor substrate having its surface forced against the polishing platen is brought into press-contact with a second pressure unit provided with a second flexible element which is small in deformation.
In the foregoing, a preferable mode is one wherein the first polishing step is performed in a manner such that a part of the second metal-film formed on the top surface of the semiconductor substrate still remains after completion of performance of the first polishing step.
Also, a preferable mode is one wherein the polishing liquid is shared by both the first and the second polishing step.
Also, a preferable mode is one wherein the polishing liquid used in the second polishing step is different from that used in the first polishing step.
Also, a preferable mode is one wherein the trench for the wiring line is constructed of: a trench portion a depth of which reaches some midpoint in film thickness of the insulation film; and, a via hole forming a through-hole of the insulation film, the through-hole extending in a direction perpendicular to the top surface of the semiconductor substrate.
Further, a preferable mode is one wherein the first metal film is made of barrier metal which is capable of forming a barrier metal film; and, the second metal film is made of copper or copper-based alloys.
Still further, a preferable mode is one wherein the barrier metal is tantalum or tantalum nitride.
According to a third aspect of the present invention, there is provided a chemical mechanical polishing apparatus provided with a polishing platen for sequentially polishing a second and a first metal film both formed on a top surface of a semiconductor substrate through an insulation film including a trench for a wiring line, wherein the first and the second metal film are sequentially formed over an entire top surface of the semiconductor substrate through the insulation film, the chemical mechanical polishing apparatus including:
a first pressure unit provided with a first flexible element which is large in deformation, the first flexible element forcing the semiconductor substrate against the polishing platen when the second metal film is polished; and
a second pressure unit provided with a second flexible element which is small in deformation, the second flexible element forcing a rear surface of the semiconductor substrate when the first metal film is polished.
In the foregoing third aspect, a preferable mode is one wherein the first flexible element which is large in deformation is constructed of an air bag filled with a pressurized fluid.
Also, a preferable mode is one wherein the first flexible element which is large in deformation is constructed of a rubber member mounted on a surface of the polishing platen.
Also, a preferable mode is one wherein the second flexible element which is small in deformation is constructed of a metal plate.
With the above configurations, it is possible to increase a ratio of removal rate of the copper film to removal by using a relatively simple construction and accordingly to prevent a dishing problem of a buried wiring line.